(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to active pixel sensor technology.
(2) Description of Prior Art
CMOS image sensors (CIS) have many advantages over CCD image sensors. Some of these are lower voltage operation, lower power consumption, compatibility with logic circuitry, random access and lower cost. Due to the increase in imager density, the area allotted to the pixels is a large percentage of the chip area. In conventional image pixels there are two levels of metal are used for interconnection. However, five metal levels are used for the peripheral logic circuits. This disparity in the metal levels between the pixel and logic regions, when combined with the large percentage of the chip area occupied by the pixels, provide for conditions in which serious loading effects are found in metal etching. These affects occur because the etch rate depends on the amount of etchable surface exposed to the etchants and are readily encountered as a result of changes in etch rate when the fraction of etchable exposed material changes during the etch.
A popular conventional active pixel based on CMOS is shown in FIG. 1. It contains one photo-diode and three n-channel MOS transistors (for reset, source follower, and row access). The “reset transistor”, 10, is used for resetting the potential of the floating-node of photo-diode 12 to Vcc. The floating-node of the photo-diode is connected to the gate of “source follower” 14, where its conductance is modulated by the floating-node potential. After reset operation, the potential of photo-diode is modulated (decreasing) by accumulating electrons generated by image light (or photons) during the “image integration” period. After turning on the row access transistor, 16, Vo is read out (one VT below the floating-node potential) as the output of the image signal. The output is essentially linear with the photo-signal (i.e. floating-node potential), which is proportional to the number of electrons generated by the image light. The number of electrons generated by the image light is in turn proportional to the area of the photodiode junction. A higher sensitivity is therefor achieved for larger area photodiodes. Consequently the photodiode occupies the largest fraction of the pixel area. This is seen in FIG. 2, which shows the layout of a typical CIS pixel. The photodiode, 12, clearly occupies the majority of the pixel area. In FIG. 2, region 18 is the active pixel area containing the pixel circuits except for the photodiode.
FIG. 3 shows a conventional CMOS image sensor chip. The image pixel area, 20, can occupy about 90% of the chip area. This area, usually arranged in the form of a grid matrix array as shown, contains photodiode regions, 48, which take up most of the area and the remaining sensor circuitry, which are placed in the areas 50, peripheral to the photodiodes. Logic circuit, are contained in the chip peripheral area, 22, which also contains metal regions, 24 used for interconnection. Logic circuits require up to five levels of metal. The layered structure of an image pixel region of a CIS is shown in FIG. 4. A photodiode, 70, is situated under a shallow trench isolation region, 30, and other components are included in region 32. All these regions are contained in or on a semiconductor substrate, 54. Only the two metal levels, 26 and 28 are required for interconnection in the image pixel region. These interconnection metal levels do not completely shield the underlying sensor devices from incoming light, which gives rise to extraneous currents and noise that affects the performance of the devices. Furthermore, the two interconnection metal levels are insufficient to adequately collimate incoming light 46 and there is cross talk to nearby sensors, as indicated in FIG. 4.
Methods of reducing loading affects arising during metal etch are disclosed in several patents. U.S. Pat. No. 5,278,105 to Eden et al. discloses a method in which dummy features are introduced to increase the percentage of material remaining after etch and thereby to reduce the loading affect. Dummy metal shaped in blocks are used by Yang et al. in U.S. Pat. No. 5,798,298 to prevent the loading affect during etching for multilevel interconnection. In U.S. Pat. No. 5,915,201 to Chang et al. dummy metal areas with sizes similar to the functional metal lines are distributed among the functional lines reducing the loading affect. Dummy metal patterns are used by Heo to reduce loading effects, as disclosed in U.S. Pat. No. 5,926,733 to Heo. Lee in U.S. Pat. No. 6,180,448 to alleviate the loading affect uses dummy storage electrodes.